module DPD(
  input    controlled_signal,        //受控信号
	input    reference_signal,         //参考信号
	input    rst,                      //复位信号（反）
	input    clk,                      //时钟源
	
	output    lead_signal_wire,             //提前信号，表示受控信号提前于参考信号出现边沿
	output    lag_signal_wire,              //滞后信号，表示受控信号滞后于参考信号出现边沿
	output    bothEdge                //上升沿触发信号，表示参考信号出现上升沿	
    );
	
wire Q;                                //异或的中间变量
reg	 K;                                //上升沿触发信号的边沿信号
reg  controlled_signal_last;
reg   reference_signal_last;
reg  controlled_signal_now;
reg   reference_signal_now;
reg  lead_signal;
reg  lag_signal;

assign lead_signal_wire = lead_signal;
assign lag_signal_wire = lag_signal;

always @(posedge clk or negedge rst)  
begin
	if(!rst)
		K <= 'd0;
	else 
		K <= reference_signal;
end	
assign	bothEdge = (reference_signal ^ K) && reference_signal;

always @(posedge clk or negedge rst)
begin
    if(!rst)
	begin
	    controlled_signal_last <= 0;
		controlled_signal_now <= 0;
		reference_signal_last <= 0;
		reference_signal_now <= 0;
	end
	else
	begin
	    controlled_signal_last <= controlled_signal_now;
		reference_signal_last <= reference_signal_now;
		controlled_signal_now <= controlled_signal;
		reference_signal_now <= reference_signal;
	end
end


always @(*)	
begin
    case({reference_signal_last,controlled_signal_last,reference_signal_now,controlled_signal_now})  
        4'b0000: 
		begin
		    lead_signal=0;
			lag_signal=0;
		end
        4'b0001: 
		begin
		    lead_signal=0;
			lag_signal=0;	
		end	
        4'b0010: 
		begin
		    lead_signal=1;
			lag_signal=0;	
		end	
		4'b0011: 
		begin
		    lead_signal=0;
			lag_signal=0;	
		end	
		4'b0100: 
        begin
		    lead_signal=0;
			lag_signal=0;
		end    
		4'b0101: 
		begin
		    lead_signal=0;
			lag_signal=lag_signal;
		end    
		4'b0110: 
		begin
		    lead_signal=1;
			lag_signal=0;
		end    
		4'b0111: 
		begin
		    lead_signal=0;
			lag_signal=0;
		end    
		4'b1000: 
		begin
		    lead_signal=0;
			lag_signal=0;
		end    
		4'b1001:  
		begin
		    lead_signal=0;
			lag_signal=0;
		end    
		4'b1010: 
		begin
		    lead_signal=1;
			lag_signal=0;
		end    
		4'b1011: 
		begin
		    lead_signal=0;
			lag_signal=0;
		end    
		4'b1100: 
		begin
		    lead_signal=0;
			lag_signal=0;
		end    
		4'b1101: 
		begin
		    lead_signal=0;
			lag_signal=1;
		end    
		4'b1110:
		begin
		    lead_signal=1;
			lag_signal=0;
    	end	
		4'b1111: 
		begin
		    lead_signal=0;
			lag_signal=0;
		end    
		default:
		begin
		    lead_signal=0;
			lag_signal=0;
		end	
    endcase	
end	

endmodule
